Open to Opportunities · Washington, DC
Hi, I'm Chaitanya
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MS in EE @ George Washington University · Ex-Synopsys · Washington, DC
Building robust silicon from RTL to signoff.
Who I Am
About Me
I'm an ASIC Digital Design Engineer with 2+ years of industry experience at Synopsys, Inc., where I built and validated I3C IP on HAPS FPGA platforms — from circuit setup through SDK release.
Currently completing my MS in Electrical Engineering (GPA: 3.96) at George Washington University, with focused coursework in VLSI Design and ASIC Testing.
I'm passionate about RTL microarchitecture, functional verification, CDC analysis, and timing closure — and actively seeking ASIC / FPGA / RTL / STA roles in the USA.
What I Work With
Technical Skills
HDL & Languages
EDA Tools
Protocols
Digital Design
Where I've Worked
Experience
ASIC Digital Design Engineer
Synopsys, Inc.
Bengaluru, India
- ▸Led FPGA Development prototyping and IP Validation in BareMetal and Linux platforms for I3C, an advancement of the I2C interface.
- ▸Built end-to-end I3C IP microarchitecture hardware validation from circuit setup through SDK release, using Synopsys ARC processor and HAPS FPGA platform via AXI tunnel, JTAG, and protocol analyzer.
- ▸Validated IPs via simulation, synthesis, regressions, bitfile generation, C-tests, and compliance testing — achieving 99% feature coverage.
- ▸Debugged critical electrical ringing issue misidentified as In-Band Interrupts (IBI); resolved by optimizing trace lengths and component placement — reducing signal feed-through by 42%.
- ▸Increased I3C payload size from 128 bytes to 64 KB by deploying High-Data-Rate (HDR) modes, improving data transmission speed by 35%.
- ▸Built FSM for vendor-specific I3C command handling and integrated it into the full protocol stack with a 4-member HW/SW team.
- ▸Migrated prototyping platform from HAPS-DX7 to HAPS100, delivering 4× faster performance at speeds up to 12.5 MHz.
Hardware Engineer
L&T Technology Services Ltd
Bengaluru, India
- ▸Conducted Board Bring-up and Circuit Board Layout in Altium, covering IC power calculation, Signal Integrity (SI), and Power Integrity (PI).
- ▸Performed AC timing analysis, wire harness, and functional test for Texas Instruments (TI) sensors in hardware lab with 100% pass results.
- ▸Used multimeters, power supplies, and logic analyzers for hands-on hardware validation.
What I've Built
Projects
Multi-Clock Domain SPI Memory Controller
SPI interface for read/write into a 256-address × 16-bit register array with multi-cycle clock domain crossing (CDC). Simulation, synthesis, and back-annotation in Synopsys DC.
Systolic Array for Matrix–Matrix Multiplication
Weight-stationary systolic array integrating 4-bit multipliers, 11-bit carry-save adders, and registers for pipelined MAC operations. Full PnR, DRC, and LVS checks.
MIPS CPU Core (Multi-Cycle)
Designed, implemented, and verified a MIPS CPU using multi-cycle microarchitecture. Constructed the full datapath and FSM-based control unit supporting the complete instruction set.
Digital Alarm Clock — RTL
Verilog-based digital alarm clock with complete simulation and synthesis flow. Demonstrates RTL design methodology from specification through gate-level netlist.
Academic Background
Education
The George Washington University
Washington, DC
Master of Science in Electrical and Electronics Engineering
Key Courses
Dayananda Sagar College of Engineering
Bengaluru, India
Bachelor of Engineering in Electronics and Communication Engineering
Key Courses
Get In Touch
Let's Connect
I'm actively seeking ASIC / FPGA / RTL / STA roles in the USA. Open to full-time positions and relocation. Let's talk.
Location
Washington, DC